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TSA0801
8-BIT, 40MSPS, 40mW A/D CONVERTER
s 8-bit A/D converter in deep submicron s s s s s s s s
CMOS technology Single supply voltage: 2.5V Input range: 2Vpp differential 40Msps sampling frequency Ultra low power consumption: 40mW @ 40MHz (10mW @ 5Msps) ENOB=7.9 @ Nyquist SFDR typically up to 67dB @ Fs=40Msps, Fin=5MHz Built-in reference voltage with external bias capability STMicroelectronics 8, 10, 12 and 14-bits ADC pinout compatibility ORDER CODE
Part Number TSA080 1CF TSA080 1CFT TSA080 1IF TSA080 1IFT EVAL0801/AA Temperature Range 0C to +70C 0C to +70C -40C to +85C -40C to +85C Package TQFP48 TQFP48 TQFP48 TQFP48 Conditioning Tray Tape & Reel Tray Tape & Reel Marking SA0801C SA0801C SA0801I SA0801I
Evaluation board
PIN CONNECTIONS (top view)
AGND
AVCC
VCCB
GNDB
AVCC
DFSB
VCCB
OEB
NC
NC
NC
DR
index c orner
48
47 46 45
44 43
42
41
40
39
38 37 36 NC 35 NC 34 NC 33 NC 32 NC 31 D0(L SB)
DESCRIPTION The TSA0801 is an 8-bit, 40MHz sampling frequency Analog to Digital converter using a deep submicron CMOS technology combining high performances and very low power consumption. The TSA0801 is based on a pipeline structure and digital error correction to provide excellent static linearity and go beyond 7.9 effective bits at Fs=40Msps, and Fin=10MHz. A voltage reference is integrated in the circuit to simplify the design and minimize external components. It is nevertheless possible to use the circuit with an external reference. Differential or single-ended analog inputs can be applied to the converter. A tri-state capability is available on the outputs. The output data can be coded into two different formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA0801 is available in commercial (0 to +70C) and extended (-40 to +85C) temperature range, in a small 48 pins TQFP package. APPLICATIONS
IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 DVCC 14 15 DVCC DGND 16 CLK 17 DGND 18 19 20 21 22 DGND NC GNDB GNDB VCCB 23 24 D7 (MSB) OR
TSA0801
30 D1 29 D2 28 D3 27 D4 26 D5 25 D6
PACKAGE
7 x 7 mm TQFP48
s s s s
Hand-held instrumentation Camcorders Computer scanners Digital communication
October 2000
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TSA0801
ABSOLUTE MAXIMUM RATINGS
Symbol AVCC DVCC VCCB IDout Tstg ESD Analog Supply voltage 1) Digital Supply voltage
1) 1)
Parameter
Values 0 to 3.3 0 to 3.3 0 to 3.3 -100 to 100 +150 2 1.5
Unit V V V mA C KV
Digital buffer Supply voltage Digital output current Storage temperature Electrical Static Discharge: - HBM - CDM-JEDEC Standard
1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V
OPERATING CONDITIONS
Symbol AVCC DVCC VCCB VREFP VREFM Parameter Analog Supply voltage Digital Supply voltage Digital buffer Supply voltage Forced top voltage reference Forced bottom reference voltage Test conditions Min 2.25 2.25 2.25 1.16 0 Typ 2.5 2.5 2.5 0 Max 2.7 2.7 2.7 AVCC 0.5 Unit V V V V V
BLOCK DIAGRAM
+2.5V
VREFP
GNDA VIN INCM VINB VREFM stage 1 stage 2 stage n Reference circuit IPOL
Sequencer-phase shifting CLK Timing Digital data correction
DFSB OEB
DR DO
Buffers
TO D7 OR
GND
2/20
TSA0801
PIN CONNECTIONS (top view)
VCCB AGND AVCC AVCC GNDB DFSB VCCB
OEB
NC
NC
DR
NC
index corner
48 IPOL VREFP VRE FM AGND VIN AGND VINB AGN D INCM AGND AVC C AVC C 1 2 3 4 5 6 7 8 9 10 11 12 13 DVCC
47 46
45
44 43
42
41
40
39
38 37 36 NC 35 NC 34 NC 33 NC 32 NC 31 D0(LS B)
TSA0801
30 D1 29 D2 28 D3 27 D4 26 D5 25 D6
14 15 DVCC DGND
16 CLK
17 DGND
18 19 DGND NC
20 GNDB
21 22 GNDB VCCB
23 OR
24 D7 (MSB)
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC DVCC DVCC DGND CLK DGND NC DGND GNDB GNDB VCCB OR Description Analog bias curr ent input Top voltage reference Bottom vo ltage referen ce Analog ground Analog input Analog ground Inverted analog input Analog ground Input common mode Analog ground Analog power supply Analog power supply Digital power supply Digital power supply Digital ground Clock input Digital ground Non connected Digital ground Digital buffer gro und Digital buffer ground Digital buffer power supply Out Of Range output 0V 0V 0V 2.5V CMOS outp ut(2.5V) CMOS outp ut(2.5V) 1V 0V 0V 1Vpp 0V 1Vpp 0V 0.5V 0V 2.5V 2.5V 2.5V 2.5V 0V 2.5V compati ble CMOS input 0V Observation Pin No 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name D6 D5 D4 D3 D2 D1 D0(LSB) NC NC NC NC NC NC DR VCCB GNDB VCCB NC NC OEB DFSB AVCC AVCC AGND Descri ption Digital output Digital output Digital output Digital output Digital output Digital output Digital output Non conne cted Non conne cted Non conne cted Non conne cted Non conne cted Non conne cted Data Ready output Digital Buffer power supply Digital Buffer ground Digital Buffer power supply Non conne cted Non conne cted Output Enable input Data Format Select input Analog power supply Analog power supply Analog ground 2.5V compatib le CMOS input 2.5V compatib le CMOS input 2.5V 2.5V 0V CMOS output (2.5V) 2.5V 0V 2.5V Observ ation CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V)
D7(MSB) Most Significa ntBit output
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TSA0801
ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V Tamb = 25C (unless otherwise specified) TIMING CHARACTERISTICS
Symbol FS DC TC1 TC2 Tod Tpd Ton Toff Parameter Sampling Frequency Clock Duty Cycle Clock pulse width (high) Clock pulse width (low) Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Data Pipeline delay Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state Test conditions Min 0.5 45 11 11 50 12.5 12.5 5 6.5 1 1 Typ Max 40 55 Unit MHz % ns ns ns cycles ns ns
TIMING DIAGRAM
N+4 N+3 N+5 N+6
N+2 N-1 N N+1
N+7 N+8
CLK
6.5 clk cycles
OEB
Tod
DATA OUT N-8 N-7 N-6
N-5
Toff
N-4 N-3 N-2
Ton
N N+1
DR
HZ state
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TSA0801
CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25C (unless otherwise specified) ANALOG INPUTS
Symbol Parameter Test conditions Min Typ 2.0 7.0 Vin@-1dBFS, FS=40Msps 100 60 Max Unit Vpp pF MHz MHz
VIN-VINB Full scale reference voltage Cin BW ERB Input capacitance Analog Input Bandwitdh Effective Resolution Bandwidth 1)
1) See parameters definition for more information
REFERENCE VOLTAGE
Symbol VREFP Parameter Top internal reference voltage Test conditions Min 0.89 Tmin= -40C to Tmax= 85C1) 0.88 1.19 Vpol Ipol Ipol VINCM Analog bias voltage Analog bias current Analog bias current Input common mode voltage Tmin= -40C to Tmax= 85C1) Normal operating mode Shutdown mode 0.46 Tmin= -40C to Tmax= 85C
1) Not fully tested over the temperature range. Guaranted by sampling.
1)
Typ 1.03
Max 1.16 1.16
Unit V V V V A A
1.27
1.35 1.36
1.18 50 70 0 0.57
100
0.66 0.66
V V
0.46
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TSA0801
CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25C (unless otherwise specified) POWER CONSUMPTION
Symbol ICCA Parameter
1)
Test conditions
Min
Typ 15.8
Max 20 21
Unit mA mA mA mA mA mA A mW mW mW C/W C/W
Analog Supply current Tmin= -40C to Tmax= 85C2)
1)
1.3
2 2
ICCD
Digital Supply Current
Tmin= -40C to Tmax= 85C2)
1)
2.1
2)
5 5
ICCB
Digital Buffer Supply Current Digital Buffer Supply Current in High Impedance Mode Power consumption in normal operation mode Power consumption in High Impedance mode Junction-ambient thermal resistor (TQFP48) Junction-case thermal resistor (TQFP48)
1)
Tmin= -40C to Tmax= 85C ICCBZ
50 48
110 60 62
1)
Pd
Tmin= -40C to Tmax= 85C2)
1)
PdZ Rthja Rthjc
43 80 18
55
1) Rpol= 18K. Equivalent load: Rload= 470 and Cload= 6pF 2) Not fully tested over the temperature range. Guaranted by sampling.
DIGITAL INPUTS AND OUTPUTS
Symbol Digital inputs VIL VIH Logic "0" voltage Logic "1" voltage 2.0 0.8 V V Parameter Test conditions Min Typ Max Unit
Digital Outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage Iol=10A Ioh=10A 2.4 -1.5 1.5 15 0.4 V V A pF
High Impedance leakage current OEB set to VIH Output Load Capacitance
ACCURACY
Symbol OE DNL INL 6/20 Parameter Offset Error Differential Non Linearity Integral Non Linearity Monotonicity and no missing codes -0.5 -1 +0.5 +1 Guaranted Test conditions Min Typ Max Unit mV LSB LSB
TSA0801
CONDITIONS AVCC = DVCC = 2.5V, Fs= 40Msps, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25C (unless otherwise specified) DYNAMIC CHARACTERISTICS
Symbol Parameter Test conditions Fin= 5MHz Fin= 10MHz Fin= 24MHz SFDR Spurious Free Dynamic Range Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz SNR Signal to Noise Ratio Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz THD Total Harmonic Distortion Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz Fin= 5MHz Fin= 10MHz Fin= 24MHz ENOB Effective Number of Bits Fin= 5MHz Fin= 10MHz Fin= 24MHz
2) 1) 2) 1) 2) 1) 2) 1) 2) 1)
Min 60 60 60 60 60 59.8 48 48 48 48 48 48 56 56 56 57 55 57 48 48 48 48 48 48 7.8 7.8 7.8 7.8 7.8 7.8
Typ 68 68 67.7
Max
Unit
dBc
dBc
48.8 48.8 48.8 dB
dB
72.5 72.5 67 dB
dB
48.7 48.7 48.7 dB
SINAD
Signal to Noise and DistortionRatio
dB
7.97 7.97 7.96 bits
bits
1) Rpol= 18K. Equivalent load: Rload= 470 and Cload= 6pF 2) Tmin= -40C to Tmax= 85C. Not fully tested over the temperature range. Guaranted by sampling.
7/20
TSA0801
DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 40Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 40Msps. Spurious Free Dynamic Range (SFDR) The ratio between the amplitude of fundamental tone (signal power) and the power of the worst spurious signal (not always an harmonic) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distorsion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD= 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between time when the analog input is initially sampled and time when the corresponding digital data output is valid on the output bus. Also called data latency. It is expressed as a number of clock cycles.
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TSA0801
EQUIVALENT CIRCUITS Figure 1 : Analog Input Circuit
AVCC=2.5V
Figure 3 : Input buffers
VCCbuf=2.5V
VIN
355.5
278.5 208.2
DFS
(or VINB)
PAD CAPACITANCE
7 pF
PA D CAPACIT ANCE
7pF
AGND=0V
commonmode
GNDbuff=0V
Figure 2 : Input clock circuit
DVCC=2.5V
Figure 4 : Tri-state output buffers
VCCbuf=2.5V
CLK
OE
DATA
GNDbuff= 0V VCCbuf =2.5V
OUT
2 mA OUTPUT BUFFER
PAD CAPACITANCE
7pF
PADCAPACITANCE 7pF
DGND=0V
GNDbuff=0V
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TSA0801
Static parameter: Integral Non Linearity Fs=40MSPS; Fin=1MHz; Icca=11mA; N=65536pts
0 .1
0.05
INL (LSBs)
0
-0 .0 5
-0 . 1
-0 .1 5 0 50 10 0 O u tpu t C o d e 150 2 00 2 50
Static parameter: Differential Non Linearity Fs=40MSPS; Fin=1MHz; Icca=11mA; N=65536pts
0 .0 8 0 .0 6 0 .0 4 0 .0 2 DNL (LSBs) 0 -0 . 0 2 -0 . 0 4 -0 . 0 6 -0 . 0 8 -0 . 1 0 50 10 0 Ou tpu t C o d e 15 0 2 00 250
Linearity vs. AVcc Fs=40MSPS; Icca=11mA; Fin=1MHz
Distortion vs. AVcc Fs=40MSPS; Icca=11mA; Fin=1MHz
-67
49.4
8 7.9 95 SNR 7.9 9
Dynamic Parameters (dB)
Dynamic parameters (dB)
-67 .5 -68 -68 .5 -69 -69 .5 -70 2.25 SFDR THD
49.3 49.2 49.1
SINAD 49 48.9 48.8 48.7 48.6 2.25 ENOB
7.9 8 7.9 75 7.9 7 7.9 65 7.9 6 7.9 55 7.9 5
2.35
2.4 5
2.55
2.65
2.35
2.4 5
2.55
2.6 5
AVCC (V)
AVCC (V)
10/20
ENOB (bits)
7.9 85
TSA0801
Linearity vs. DVcc Fs=40MSPS; Icca=11mA; Fin=1MHz Distortion vs. DVcc Fs=40MSPS; Icca=11mA; Fin=1MHz
8 7.99 7.98 EN0B 49.5 49.3 49.1 SINAD 48.9 48.7 48.5 2.25 2.3 5 2.4 5 2.55 2.65 SNR
Dynamic parameters (dB)
49.9 Dynamic parameters 49.7
-61 -63 -65 -67 -69 -71 -73 -75 2.25 2.35 2.45 2.5 5 2.65 SFDR THD
7.96 7.95 7.94 7.93 7.92 7.91 7.9
DVCC (V)
ENOB (bits)
7.97
DVCC (V)
Linearity vs. VccB Fs=40MSPS; Icca=11mA; Fin=1MHz
Distortion vs. VccB Fs=40MSPS; Icca=11mA; Fin=1MHz
50
8 7.99 7.98 ENOB
-65
Dynamic parameters (dB)
49 .9 49 .8 49 .7 49 .6 49 .5 49 .4 49 .3 49 .2 49 .1 49 2.25 2.35 SINAD 2.45 2.5 5 2.65 SNR
Dynamic parameters (dB)
-66 -67 -68 -69 -70 -71 -72 -73 -74 -75 2.25 2.35 2.45 2.5 5 2.65 THD SFDR
7.96 7.95 7.94 7.93 7.92 7.91 7.9
VCCB (V)
ENOB (bits)
7.97
VCCB (V)
Linearity vs. Fs Icca=11mA; Fin=5MHz
Distortion vs. Fs Icca=11mA; Fin=5MHz
52
8 ENOB 7.9 7.8
-50
Dynamic parameters (dB)
51.5 51 50.5 50 49.5 49 48.5 48 47.5 47 20 30 40 50 60 SINAD SNR
Dynamic parameters (dB)
-55 -60 THD -65 -70 -75 -80 20 30 40 50 60 SFDR
7.7 7.6 7.5 7.4 7.3 7.2
Fs (MHz)
ENOB (bits)
Fs (MHz)
11/20
TSA0801
Linearity vs. Fs Icca=11mA; Fin=15MHz Distortion vs. Fs Icca=11mA; Fin=15MHz
-50
52
8 ENOB 7.9 7.8
Dynamic parameters (dB)
-55 -60 THD -65 -70 -75 -80 -85 20 30 40 50 60 SFDR
Dynamic parameters (dB)
51 50 SNR 49 SINAD 48 47 46 20 30 40 50 60
7.6 7.5 7.4 7.3 7.2 7.1 7
Fs (MHz)
Fs (MHz)
Linearity vs. Fin Fs=40MSPS; Icca=11mA
Distortion vs. Fin Fs=40MSPS; Icca=11mA
50
8 ENOB 7.95 7.9 SNR 7.85 7.8 7.75 7.7 0 20 40 60
-50
Dynamic parameters (dB)
49.8 49.6 49.4 49.2 49 SINAD 48.8 48.6 48.4
Dynamic parameters (dB)
-55
ENOB (bits)
-60
T HD
-65
SFDR
-70
-75 0 20 40 60
Fin (MHz)
Fin (MHz)
Linearity vs. Temperature Fs=40MSPS; Icca=11mA; Fin=5MHz
Distortion vs. Temperature Fs=40MSPS; Icca=11mA; Fin=5MHz;
50
8 Dynamic Parameters (dB)
ENOB
90 85 80 T HD 75 70 65 60 55 -50 0 50 100 SFDR
Dynamic Parameters (dB)
49 .8 49 .6 49 .4 49 .2 49 48 .8 48 .6 48 .4 48 .2 48 -50 0 50 100 SINAD SNR
7.95 7.9 7.85 7.8 Temperature (C)
Temperature (C)
12/20
ENOB (bits)
7.7
TSA0801
Power spectrum Fs=40MSPS - Icca=11mA - Fin=1MHz
0 -20 -40 -60 -80 -100 0 2 4 6 8
Power spectrum (dBm)
Frequency (MHz)
10
12
14
16
18
Power spectrum Fs=40MSPS - Icca=11mA - Fin=10MHz
0 -20 -40 -60 -80 -100 0 2 4 6 8
Power spectrum (dBm)
Frequency (MHz)
10
12
14
16
18
Power spectrum Fs=40MHz - Icca=11mA - Fin=50MSPS
0 -20 -40 -60 -80 -100 0 2 4 6 8
Power spectrum (dBm)
Frequency (MHz)
10
12
14
16
18
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TSA0801 APPLICATION NOTE
DETAILED INFORMATION The TSA0801 is a High Speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 9 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each 8 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the conversion delay. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each OPERATIONAL MODES DESCRIPTION Inputs Analog input differential level (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE X Data Format Select (DFSB) When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. This results in lower consumption while the converter goes on sampling.
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stage. The corrected data are outputted through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the Data Ready signal. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA0801 is pin to pin compatible with the 10bits/25Msps TSA1001, the 10bits/50Msps TSA1002 and the 12bits/50Msps TSA1201. This ensures a conformity within the product family and above all, an easy upgrade of the application.
Outputs DFSB H H H L L L X OEB L L L L L L H OR H H L H H L HZ DR CLK CLK CLK CLK CLK CLK HZ Most Significant Bit (MSB) D9 D9 D9 Complemented D9 Complemented D9 Complemented D9 HZ
When OEB is set to low level again, the data is then valid on the output with a very short Ton delay. The timing diagram summarizes this operating cycle. Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at '0' or all the data being at '1'. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range.
TSA0801
Data Ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D9). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As digital output, DR goes in high impedance state when OEB is asserted to High level as described in the timing diagram. DRIVING THE ANALOG INPUT Differential inputs The TSA0801 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 5 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.56V. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1 transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp. Figure 5 : Differential input configuration
330pF
amplitude, or it must be increased to 0.9V to support a 2Vpp input amplitude. Performances are better when using a 2Vpp signal. Figure 6 : Single-ended input configuration
Signal source
100nF
VIN
50
TSA0801
VINB INCM
10nF
470nF
0.9V
REFERENCE CONNECTION Internal reference In the standard configuration, the ADC is biased with the internal reference voltage. VREFM pin is connected to Analog Ground while VREFP is internally set to a voltage of 1.03V. It is recommended to decouple the VREFP in order to minimize low and high frequency noise. Refer to Figure 7 for the schematics. Figure 7 : Internal reference setting
Analog source
ADT1-1 1:1 VIN
100pF
1.03V
330pF
10nF 470nF
50
TSA0801
VINB INCM
VIN
VREFP
TSA0801
VINB VREFM
330pF
10nF
470nF
Single-ended input configuration Some applications may require a single-ended input which is easily achieved with the configuration reported on Figure 6. In this case, it is recommended to use an AC-coupled analog input and connect the other analog input to the common mode voltage of the circuit (INCM) so as to properly bias the ADC. The INCM may remain at the same internal level (0.56V) thus supporting only a 1Vpp of input
15/20
External reference It is possible to use an external reference voltage instead of the internal one for specific applications requiring even better linearity or enhanced tem0801perature behavior. In this case, the amplitude of the external voltage must be at least equal to the internal one (1.03V). Using the STMicroelectronics Vref TS821 leads to optimum
TSA0801
performances when configured as shown on Figure 8. Figure 8 : External reference setting The TSA0801 will combine highest performances and lowest consumption at 40Msps when Rpol is equal to 18k. At lower sampling frequency range (< 10Msps), this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. As an example, 10mW total power consumption is achieved at 5 Msps with Rpol equel to 390k. The table below sums up the relevant data. Total power consumption optimization depending on Rpol value
Fs (Msps) Rpol (k) Optimized power (mW) 5 390 10 15 40 25 25 25 35 40 18 40
1k
330pF
10nF 470nF
VCCA VREFP VIN
TSA0801
VINB VREFM
TS821
external reference
At 15Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved of up to 2dBc on SFDR and 0.3dB on SINAD. At 40Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved of up to 1dBc on SFDR and 0.6dB on SINAD. This can be very helpful for example for multichannel application to keep a good matching among the sampling frequency range. Clock input The quality of your converter is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The duty cycle must be between 45% and 55%. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5Msps, before applying the supply voltages. Power consumption optimization The internal architecture of the TSA0801 enables to optimize the power consumption according to the sampling frequency of the application. For this purpose, a resistor is placed between IPOL and the analog Ground pins.
Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is mandatory for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD).
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TSA0801
EVAL0801 evaluation board The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 10. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: SFSR=+0.2dB for static parameters.SFSR=-0.5dB for dynamic parameters.
Figure 9 : Analog to Digital Converter characterization bench
Power
HP8644B Sine wave Generator
Vin
ADC evaluation board
ck
data
Logic Analyzer
dataready
TLA704 HP8133A Pulse Generator
HP8644B
Sine Wave Generator
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J9 DFSB J11 1 2 1 2 1 2 VCCB2 C34
+
J10 OEB J13 1 2
J17 VDDBUFF3V
R10 47K R11 47K R12 47K R13 47K C16 AVCC 470nF C15 470nF C27 10nF C25 J6 DR 330pF DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 OR 330pF R14 R15 R16 R17 R18 R19 47K 47K 47K 47K 47K 47K 10nF C26 10nF C14 R2 1K 330pF 470nF C39 C28 VCCB1 47 C37
J2 Raj1 47K
1 2
VrefP
J5
1 2
VrefM C31 C13 C12 C30 330pF 470nF 10nF 330pF AGND AVCC AVCC DFSB OEB NC NC 2.5VCCBUFF GNDBUFF 2.5VCCBUFF DR D0 C11 10nF 48 47 46 45 44 43 42 41 40 39 38 37
J1 Vin
1
T2
6
C32
Figure 10 : TSA0801 evaluation board schematic
R1 50 3
2
470nF
4 T2-AT1-1WT 8-14bits ADC TSA0801 74LCX573
C1 100pF
1 2
1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE 20 19 18 17 16 15 14 13 12 11
J7
C10
C9
C8
1 2 C3 470nF 10nF 330pF C4 C2
470nF 10nF
330pF
Regl com mode J8
C7
C6
C5
1 2 13 14 15 16 17 18 19 20 21 22 23 24
Mes com Mode J12 74LCX573 C38 C29 6 2 4
+
DVCC DVCC DGND CLK DGND NC DGND GNDBUFF GNDBUFF 2.5VCCBUFF OR D13
470nF 10nF
330pF
AVCC
1 2 3 4 5 6 7 8 9 10 11 12 Ipol VrefP VrefM AGND Vin AGND VINB AGND INCM AGND AVCC AVCC D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 20 19 18 17 16 15 14 13 12 11 36 35 34 33 32 31 30 29 28 27 26 25
2 1
AVCC
+
C42 47F 470nF C40
J19 C20 10FC17
C41 10F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32PIN
1 2
AGND
J20 1 3 330pF C21 R3 50 10nF C19 470nF C24 10 VCCB1
+
1 2 10nF C22 470nF C23 10
+
T1 T2-AT1-1WT 330pF C18 10nF C33 330pF
DGND
J21
1 2
GndB2 C36 47 2 1 J4 CLJ/SMB J18 VccB1 2 1 C35 47
J22
1 2 2 1 J15 DVCC
GndB1 J16 CON2
TSA0801
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TSA0801
Figure 11 : circuit board - Top side silkscreen
Printed circuit board - List of components
P a rt T ype 10 u F 10 u F 10 u F 10 u F 10 0 pF 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 10 n F 1K 3 2 P IN 330pF 330pF D e s i gn F o o t p r in t a to r C 24 C 23 C 41 C 29 C1 C 12 C 39 C 15 C 40 C 27 C4 C 21 C 31 C6 C9 C 18 R2 J6 C 25 C 26 12 10 12 10 12 10 12 10 603 603 603 603 603 603 603 603 603 603 603 603 603 ID C 3 2 603 603 P a rt T ype 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 4 7uF 4 7uF 4 7uF 4 7uF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF D e s ig n F o o t p r in t a to r C 33 C 20 C8 C2 C5 C 11 C 30 C 17 C 14 C 36 C 34 C 35 C 42 C 22 C 32 C 37 C 38 C 13 C 28 C 10 603 603 603 603 603 603 603 603 603 CA P CA P CA P CA P 805 805 805 805 805 805 805 P a rt T yp e 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 50 50 D e s i gn F o o t p r in t a to r C7 C 16 C 19 C3 R 12 R 14 R 11 R a j1 R 10 R 19 R 13 R 15 R 16 R 17 R 18 R3 R1 805 805 805 805 603 603 603 VR 5 603 603 603 603 603 603 603 603 603 T S SO P 20 T S SO P 20 S IP 2 P a rt T ype A VC C C LJ / S M B A GN D D FSB D GN D D VC C G nd B 1 G nd B 2 D e sign at o r J 12 J4 J 19 J9 J2 0 J 15 J2 2 J2 1 F IC H E 2 M M S M B /H F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M F IC H E 2 M M ADT ADT F IC H E 2 M M F IC H E 2 M M S M B /H F IC H E 2 M M F IC H E 2 M M T QF P 4 8 F o o t pr in t
M es c o m m o de J8 O EB J 10
R e gl c o m m o de J 7 T 2 - A T 1- 1W T T 2 - A T 1- 1W T V cc B 1 V D D B UF F3 V V in V re f M V re f P T SA 0 8 01 T2 T1 J 18 J 17 J1 J5 J2 U1
7 4L C X 5 73 U 3 7 4L C X 5 73 U 2 C ON2 J 16
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TSA0801
PACKAGE MECHANICAL DATA: 48 PINS - PLASTIC PACKAGE
A A2 48 1 e 37 36 A1 0,10 mm .004 inch
SEATING PLANE B E3 E1
12 13 D3 D1 D 24
25
c
L1
L
E
0,25 mm .010 inch
GAGE PLANE
K
Millimeters Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 Typ. Max. 1.60 0.15 1.45 0.27 0.20
Inches Min. 0.002 0.053 0.007 0.004 Typ. Max. 0.063 0.006 0.057 0.011 0.008
1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00
0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039
0.45
0.75
0.018
0.030
0 (min.), 7 (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infring ement of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change witho ut notice. This publ ication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life suppo rt devices or systems withou t express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www. st.com
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